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The PLL generates two system clock outputs, sysclk_2x and sysclk_2x_180, that are twice. the frequency of the desired memory clock (for example, for a 667 Mb/s DDR2 interface. with a memory clock equal to 333 MHz, the system clocks are set to 667 MHz) and. 180 degrees out of phase from each other.

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Spartan-6 FPGA Memory Controller User Guide This guide describes the Spartan-6 FPGA memory controller block, a dedicated embedded multi-port memory controller that greatly simplifies interfacing Spartan-6 FPGAs to the most popular memory standards. Spartan-6 FPGA PCB Designer's Guide This guide provides information on PCB design for Spartan-6 ...